Design of Half Adder Domino Circuit Using Sleep and Twist-Connected Transistors With Dual Keeper

Abstract

In this paper, two circuits, namely Half Adder with twist-connected transistors based NOT (T-NOT) gate and Sleep Transistor (HTS) and Half Adder with T-NOT, Sleep Transistor, and Dual Keeper (HTSD) are presented, in order to achieve low power consumption and high speed. The twist-connected transistors provide small-swing at output voltage levels results in the reduction of power consumption. Further, the high threshold sleep transistor helps in reducing the leakage power and overall power consumption but at the cost of an increase in delay. The use of a dual keeper as a substitute for a single keeper helps in minimizing the loop gain of the output feedback circuit, which helps in reducing the delay variability. Thus, an improvement in PDP by 38.96 percent and 45.45 percent in Half Adder with T-NOT and sleep transistor (HTS) and Half Adder with T-NOT, sleep transistor, and dual keeper (HTSD) is achieved as compared to Half adder with T-NOT gate.