Abstract
Abstract In this paper design and simulation of a 4.3 - 5.4 GHz LC digitally controlled oscillator (LC DCO) in IBM 7RF 0.18 μm CMOS technology are presented. Wide gigahertz tuning range is achieved by using two LC DCOs, sharing same structure. DCO is made of one NMOS negative impedance transistor pair and LC tank, which consists of high quality inductor and two switched capacitor arrays for coarse and fine frequency tuning. Coarse and fine tuning switched capacitor arrays are controlled using 6-bit and 3-bit binary words. To increase available frequency values, frequency divider is used. Structure of frequency divider is based on extended-true-single-phase-clock flip-flops. Divider is made of eight divide-by-2 cells connected in daisy chain, thus division values from 2 to 256 are available. Wide tuning range and high division values allows using such DCO with frequency divider in multi-standart transceivers. Whole device is supplied from a single 1.8 V voltage source. At highest frequency proposed device draws 90 mA current including all buffers. Phase noise is −116.4 dBc/Hz at 1 MHz offset from 5.44 GHz carrier. Designed dual DCO and frequency divider occupies about 0.4mm×0.5mm of chip space and whole chip, including pads, occupies 1.5mm × 1.5mm area of silicon.
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