Abstract
Digital finite impulse response filters has a lot of arithmetic operation. Arithmetic operation modules such as adder and multiplier modules consume much power, energy and area in general. In order to reduce the area, delay and power consumption the multiplier module in FIR (finite impulse response filter) architecture is replaced by SMB (sum to modified booth) re-coder. . SMB performs direct recoding of sum of two numbers in its modified booth form. Modified booth is a prevalent form used in multiplication; it reduces the number of partial products into half. The proposed design for FIR filters have been designed using Verilog HDL and synthesized, implemented using Xilinx ISE and Modelsim.
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