Abstract
In this paper, an area-efficient FFT processor is proposed for IEEE 802.16m mobile WiMAX systems. The proposed scalable FFT processor can support the variable length of 512, 1024, 2048 and 4096. By reducing the required number of non-trivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput. The proposed FFT processor was designed in hardware description language (HDL) and synthesized to gate-level circuits using 0.18um CMOS standard cell library. With the proposed architecture, the gate count for the processor is 49K and the size of memory is 96Kbits, which are reduced by 12% and 26%, respectively, compared with those of the 4-channel radix-2 MDC (R2MDC) FFT processor.
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