Design of fast vedic multiplier with fault diagnostic capabilities

Abstract

Multipliers are the important block in digital signal processing, high speed arithmetic logic and accumulate units. Because of the increasing limitations on delay, the importance of faster multiplication is getting increasing. For enhancing the speed of the multiplier design, many new techniques are being worked upon on the multiplier. The Vedic multiplier depends on the Urdhava-Tiryakbhyam sutra is the fastest and low power multiplier. The difficulty come arises for the purpose of testing the devices and their application system increases due to continue increases in complexity of FPGAs. BIST technique in an FPGA system of the configurable nature of these devices takes advantages to obtain an economical and very efficient testing technique by creating the testing circuits within the FPGA itself. The 64 bit Vedic multiplier design is implemented. This Vedic multiplier design is encoded in Verilog and synthesized. That synthesized design is then simulated by using Xilinx ISE 13.1. The 4 bit Vedic multiplier along with BIST is designed and implemented for the purpose of testing the multiplier circuit.