Abstract
In this paper, the design of high-fan-in CMOS multiplexers based on the heterogeneous-tree approach is discussed. In particular, a strategy to minimize the delay of multiplexers is developed that accounts for the interconnect parasitics from the beginning; thereby extending the previous results introduced in M. Lim (2000) which did not consider the effect of interconnects. The design criteria derived are very simple, and are shown to be strongly affected by interconnects, as one expects in current deep-submicron (DSM) VLSI circuits. It is also shown that neglecting parasitics in the multiplexer optimization can lead to speed degradation as high as 80%. The results are validated through post-layout simulations on a 90-nm CMOS process.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
