Design of energy efficient approximate subtractors and restoring dividers for error tolerant applications

Abstract

Approximate computing has emerged as a promising design technique exclusively for error-resilient applications such as multimedia, digital signal processing, and embedded systems. Approximate computing is appropriate for arithmetic circuits like subtractors and dividers. This present study proposes simplified approximate subtractors based on logic level reduction. High-speed approximate ripple borrow subtractors are designed to accomplish energy and area efficiency. Novel approximate restoring dividers by means of the triangle replacement technique and horizontal replacement techniques are projected. Detailed hardware and accuracy analysis are performed at 45 nm technology node using Cadence Genus Synthesis Solution. The proposed designs offer improved performance in terms of power, delay, and area than the existing design techniques. Error metric evaluation of the proposed designs shows better MED, NMED, and MSE values. Variation detection in image processing is proven for the efficiency of the proposed designs and has a minimal impact on the output quality.