Design of Embedded m-out-of-n Code Checkers Using Complete Parallel Counters

Abstract

Self-testing m-out-of-n code checkers are often designed using parallel counters. Each code word is partitioned into two parts. The ones of both parts are counted by two parallel counters or similar circuits and the obtained numbers, after a correction if necessary, are evaluated using another checker. In this paper this checker design method is extended such that the obtained checkers achieve the self-testing property under very weak conditions. It is only required that no checker input gets a constant signal and that the code words occur in a random order so that the checkers can be used as embedded checkers. The basic building blocks of the checkers are two identical parallel counters that only consist of full adders of which some have a special architecture. The obtained checkers have in most cases a much smaller hardware size than previously known embedded m-out-of-n code checkers. The proposed design method that works for all m-out-of-n codes is further extended to make the checkers programmable, i.e. the same m-out-of-n code checker can be used for different values of m.