Design of Efficient VLSI Architecture and Implementation of Power-Optimized Turbo Decoder for LTE Networks

Abstract

This chapter is about model, design, and application specific integrated circuit (ASIC) implementation to optimize turbo decoder using standard cell library of complementary metal oxide semiconductor (CMOS). Various constraints like channel noise, number of iterations, and frame length performance are analyzed and estimated through reference models. Register transfer language (RTL) model for encoder and decoder is developed, simulated, and synthesized by hardware description language (HDL). The ASIC implementation with various performance parameters like power and speed are considered to evaluate the proposed algorithm on decoder blocks. In the proposed low power turbo decoder, novel techniques like clock gating and adaptable iteration methods are used. This work proved the energy efficiency through elimination of unwanted iteration and early stopping mechanism. The results of the chapter are compared with other competent researches, and it shows that power dissipation is reduced by 34% with adaptable data rates for LTE standard wireless applications.