Abstract
The sequential circuit designed was Look-Ahead Transformation based LFSR in which a hardware complexity was present and it may limit their employ in many applications. The design of efficient LFSR for BCH encoder using TePLAT (Term Preserving Look-Ahead Transformation) overcame this limitation by opening the employ of minimizing the iteration bound and hardware complexity in wide range of applications. A TePLAT convert LFSR formulation behaves in the same way to achieve much higher throughput than those of a native implementation and a Look-Ahead Transformation-based.
Highlights
Linear Feedback Shift Register is used to generate test vectors
Some generator polynomials used on modern wireless communication applications are summarized in Tables 1 and 2 [7], [8] respectively.Traditionally Linear Feedback Shift Register (LFSR) can be implemented in hardware
The second approach seeks to reformulate LFSR algorithm so that inherent bit-level parallelism afforded by a word-based microarchitecture may be fully exploited [4]
Summary
Linear Feedback Shift Register is used to generate test vectors. It uses feedback and modifies itself on every rising edge of clock. Some generator polynomials used on modern wireless communication applications are summarized in Tables 1 and 2 [7], [8] respectively.Traditionally LFSR can be implemented in hardware. The main contribution of this work is on exploiting the low overhead property of term-preserving look-ahead transformation (TePLAT) which guarantees the number of terms of the transformed generator polynomial will remain unchanged [8]. This term preserving property makes it feasible to apply TePLAT aggressively to achieve maximum throughput rate with respect to a particular micro architecture discussed in the context of parallel recurrent equations. The speedup factor varies from 1.5 to 18 depending on the structure of the generator polynomials
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