Abstract
This paper proposed a temperature adaptive refresh circuit for traditional memory with fixed refresh frequency, high refresh power consumption at low temperature and low refresh frequency at high temperature. The 2T core storage unit combining with the existing CMOS process and circuit is taking as the research object, considering the characteristics of temperature rising, leakage current increasing, information holding time shortening, and the various constraints between the area, power consumption and other performance, this paper proposes to add the same redundant unit as the storage array to the storage array as the temperature monitoring circuit to realize the adaptive refresh function, and designs the core circuit. The simulation results show that the design of SMIC 0.09 um standard CMOS process fully meets the requirements of memory adaptive refresh.
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