Design of DRFM-based Several Radar Targets Simulator Using FPGA

Abstract

The paper describes a general design of a modern radar target simulator based on digital radio frequency memory (DRFM) technology. Such a device can be used to test radars under development and assess their stability in conditions of electronic countermeasures. The simulator is optimized to start preparing the first response right after the detection of the probing signal. The device is also adaptive to the radar signal's pulse width, so it can generate several false targets with independent ranges and velocities when working with pulse radar under test, or one false target in the case of continuous-wave radar. The algorithms of range and velocity simulation are elaborated as well as the general simulator operation algorithm. The frequency shift module for the simulator is implemented in Xilinx System Generator and the VHDL code. A comparison of FPGA resource utilization for these implementations is performed.