Design of distributed arithmetic based reconfigurable filters

Abstract

Digital signal processing techniques are widely used for a large number of applications with digital filters being considered as one of the basic elements. Digital filter design involves several multiply-and-accumulate (MAC) operations, which consume a large amount of hardware resources and computation cost. Distributed Arithmetic (DA) approach is proposed in literature as an alternative and efficient technique for MAC operation based designs. Similarly, reconfigurable computing possesses the benefits of both worlds, i.e., flexibility of software and high performance of hardware using flexible high speed computing fabric such as FPGA for efficient use of hardware resources. In this paper, design of FIR filters using the concepts of distributed arithmetic and reconfigurable computing is proposed. Two reconfigurable architectures are proposed and implemented on an SRAM based Xilinx FPGA board. The performance of proposed design is evaluated with and without reconfiguration architectures and their results are reported. It is observed that the proposed reconfigurable design saved 41.6–86.9% of hardware resources and 67.92% of power over the conventional non-reconfigurable design.