Abstract
This chapter presents the analysis and design of continuous-time ΔΣ modulators (CTΔΣMs) with a focus on single-loop topology. The methodology of mapping the noise transfer function (NTF) from discrete-time to continuous-time is explained with a design example of a fifth-order CTΔΣM. The anti-aliasing characteristics of feedback and feedforward loop filter topologies are compared. The effects of non-idealities such as the excess loop delay (ELD) and the feedback DAC’s clock jitter on the performance of CTΔΣMs are discussed. A 75-MHz single-loop CTΔΣM prototype is presented as a design example. It was fabricated in a low-power 40-nm CMOS technology, employing a broadband low-power highly efficient common-gate summing stage. This knowledge on single-loop CTΔΣMs is fundamental for the analysis and design of MASH CTΔΣMs.
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