Design of Compact Reliable Energy Efficient Read Disturb Free 17T CNFET Ternary S-RAM Cell

Abstract

This paper proposes a read disturb-free, ternary SRAM cell utilizing 17 Carbon Nanotube Field-Effect Transistors (CNFET). The proposed ternary SRAM cell works on two voltage levels and stores three high, low, and middle voltage levels. The proposed SRAM is energy efficient as the Power Delay Product (PDP) is less during the write and read operations to the past proposed designs. The proposed memory cell underwent temperature and process variations. The proposed ternary memory cell is least affected by temperature and process variations. The proposed ternary SRAM cell proved robust against the diameter of carbon nanotube ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$D_{CNT}$ </tex-math></inline-formula> ), and the channel length of the CNFET ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L_{ch}$ </tex-math></inline-formula> ) variation in the Monte-Carlo analysis. According to the existing layout design rules of CNFET, the proposed SRAM cell acquires minimum area compared to previously proposed designs.