Abstract
The paper presents the developed systematic approach to design and size of analog CMOS circuits in subthreshold region of operation by using appropriate pre-designed charts. The methodology is illustrated by analysis, sizing and simulation of current mirror operational transconductance amplifier (OTA) implemented in 16nm ultra-deep submicron CMOS technology. For this purpose, first the basic parameters and characteristics of the 16nm CMOS transistors are discussed and presented by charts. Next, an example of designing the current mirror OTA is developed. The relations between the basic design and the circuit parameters of the OTA are analyzed. Design considerations for sizing the circuit in 16nm CMOS technology are discussed and an appropriate sizing methodology is proposed. An illustrative example is presented. The results from sizing and simulation of the examined current mirror OTA are analyzed and generalized.
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