Design of Basic Logic Gates Using Carbon Nano Tube Field Effect Transistor and Calculation of Figure of Merit

Abstract

Carbon Nano tube Field Effect Transistor (CNTFET) is extensively planned for probable substitutes to traditional MOSFET. This paper presents effective design of CNTFET based digital logic gates and associated with current CMOS technology. The designs equally exhibited for CNTFET and CMOS technology, using Stanford University CNTFET model and PTM (Predictive Technology Model) independently. The compacted SPICE model is used for design and simulations of CNTFET based circuits. The typical model is designed for CNTFET which is same as MOSFET and consists of multiple carbon Nano tube. HSPICE simulation for the basic logic gates designed using Stanford University CNTFET model and PTM technologies and output performances have been extensively calculated with varying power supply with constant temperature. The power consumption and total delay of basic logic gates is calculated by substituting the CNTFET instead of MOSFET.