Design of Barrier Network of Dawning 5000 High Performance Computer

Abstract

To lower barrier operation's latency and improve large-scale parallel applications' efficiency in Dawning 5000 system,this paper proposes a hardware-based accelerating solution to barrier.The design,which implements tree-based barrier by enhancing Dawning 5000 switch chip,has features of low latency,high scalability,high reliability,and high serviceability.Dawning 5000 barrier network supports 16 concurrent barrier operations.Compared with related works in Fat-tree topology,it is a more proper solution.In ideal situation,the barrier operation of 1024 nodes can be finished within 1.7 microseconds.Based on characteristics of barrier reducing and distributing,two different mechanisms are used to guarantee reliability.The prototype system of proposed design has been verified on FPGA platform.