Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications

Abstract

In this brief, based on upset physical mechanism together with reasonable transistor size, a robust 10T memory cell is first proposed to enhance the reliability level in aerospace radiation environment, while keeping the main advantages of small area, low power, and high stability. Using Taiwan Semiconductor Manufacturing Company 65-nm CMOS commercial standard process, simulations performed in Cadence Spectre demonstrate the ability of the proposed radiation-hardened-by-design 10T cell to tolerate both $0~\rightarrow ~1$ and $1~\rightarrow ~0$ single node upsets, with the increased read/write access time.