Design of anti-key leakage camouflage gate circuit for reverse engineering based on dummy vias

Abstract

The safety of integrated circuit design has become a big challenge due to overbuilding, IC (Integrated Circuit) piracy, hardware Trojan, reverse engineering, and other attacks. Over the past decades, the demand for hardware security is increased continually in an integrated circuit. In this paper, we propose a new design of anti-key leakage camouflage gate for reverse engineering based on dummy vias. The design achieves the layout-level camouflage by using XOR, XNOR, buffer and inverter through via’s realness, followed by extracting the camouflaged circuit’s feature information to generate standard physical library. They are inserted into the circuit netlist to prevent the key leakage of IP solidification. The circuit is verified by TSMC 65 nm process and tested in ISCAS benchmark circuit. The results show that the newly-designed circuit attains 99% similarity in placing and routing in the layout, suggesting that the security of the hardware circuit can be greatly improved.