Design of an Static Reconfiguration Based on FPGA System

Abstract

Aiming at the problem of limited logical resources of FPGA and low rates of internal resource utilization, the design of the static reconfiguration system was introduced in this paper. Based on the structure of CPLD matching FPGA, the static reconfiguration system is able to enhance the scalability of the FPGA device. Major functionality in the static reconfiguration system is accomplishing field reconfiguration of the FPGA device without PC. Users are able to flexibly change the different configuration files in FPGA for that the internal resources of FPGA are occupied by the configuration files of different function at different times. The experimental results showed that the system achieved dynamic switching between different logic function and time division multiplexing of internal resources. The generality of FPGA and the rates of internal resource utilization were improved and the power dissipation was reduced by this design.