Design of an L1 band low noise single-chip GPS receiver in 0.18 μ m CMOS technology

Abstract

This article presents an L1 band low noise integrated global positioning system (GPS) receiver chip using 0.18 μm CMOS technology. Dual-conversion with a low-IF architecture was used for this GPS receiver. The receiver is composed of low noise amplifier (LNA), down-conversion mixers, band pass filter, received signal strength indicator, variable gain amplifier, programmable gain amplifier, ADC, PLL frequency synthesizer and other key blocks. The receiver achieves a maximum gain of 105 dB and noise figure less than 6 dB. The variable gain amplifier (VGA) and programmable gain amplifier (PGA) provide gain control dynamic range over 50 dB. The receiver consumes less than 160 mW from a 1.8 V supply while occupying a 2.9 mm 2 chip area including the ESD I/O pads.