Design of an efficient VLSI architecture for 2-D discrete wavelet transforms

Abstract

We present a VLSI architecture for the separable two-dimensional discrete wavelet transform (DWT) decomposition. Using a computation-schedule table, we show how the proposed separable architecture uses only a minimal number of filters to generate all levels of DWT computations in real time. For the computation of an N/spl times/N 2-D DWT with a filter length L, this architecture spends around N/sup 2/ clock cycles, and requires 2NL-2N storage units, 3L multipliers, as well as 3(L-1) adders.