Design of an array processor for image processing

Abstract

We discuss the design of an array processor that permits parallel, conflict-free access and alignment of various N-vectors (e.g., rows, columns, contiguous blocks, and distributed blocks), for image processing. The ability to meet these requirements depends on skewing schemes for mapping an N × N array of image points into N parallel memories. We present an efficient nonlinear skewing scheme upon which the design of the array processor is based. The resulting array processor has the advantage of being both simple and efficient in two important aspects of the system. The addressing hardware for the parallel memories consists of O(log N) gates, and can calculate simultaneously N local addresses in O(1) time. Furthermore, the multistage interconnection network consists of O( N log N) gates and is able to align any of these vectors with a single pass through the network using the simplest control structure, namely, individual-stage control. Organization of the memory system is discussed, and construction of the interconnection network is given.