Abstract

Following the considerable development of big data and the need for real-time information processing, the recent computing paradigm changed from centralized intelligence on cloud computing to the distributed intelligence on Edge Computing. On the algorithm layer, Artificial Intelligence (AI) has been applied in different areas related to intelligent-edge applications. In this type of application, consumption and speed present essential challenges when designing hardware-level architecture on the embedded systems. In particular, an Edge Computing System (ECS) must be an energy efficient, compact, and fast component integrated into edge devices. Miniaturization has been happening at a steady pace for the last years. However, the MOS transistor size has been slowly reaching the physical limit. In this paper, we propose a Quantum Cellular Automata clock-phase-based technique for the design of the proposed ALU module. The obtained results using the QCA architecture designer exhibit better performances over the existing designs in terms of size, cell number, cost, latency, and power consumption. We have also used QCAPro software for power consumption estimation. The results show the effectiveness of the design in terms of cost and power.

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