Design of Adiabatic Logic Circuits using FinFET 18nm Technology

Abstract

Energy efficient and secure IOT devices have an increase in demand with the emergence of Internet of Things (IoT). For example, IoT devices such as Wireless Sensor Nodes (WSN) and Radio Frequency Identification (RFID) tags employ AES cryptographic module which are susceptible to Differential Power Analysis (DPA) attacks. Crytographic devices become susceptible to DPA attacks due to the increase in leakage power with the scaling of technology. The FinFET based Adiabatic Logic Circuits are energy efficient and consume low power as compared to normal FinFET circuits. The proposed adiabatic logic is used to design logic gates such as buffers, XOR/XNOR, and AND/NAND circuits. The circuits have been designed using FinFET 18nm technology. The average power of the circuits has been computed and also the output Energy loss of the circuits has been calculated. For the Buffer the Average power consumption was found to be 4.331uW without adiabatic logic and 1.840uW with Adiabatic logic. The reduction of power is 57.51%.For the AND/NAND circuit Average power consumption was found to be 4.479uW without Adiabatic logic and 2.356uW with Adiabatic logic. The reduction of power is 47.39 % For the XOR/XNOR circuit Average power consumption was found to be 7.778uW without adiabatic logic and 4.428uW with Adiabatic logic. The reduction of power is 43.07 %.