Abstract
The design of a wide-band voltage-controlled oscillator (VCO) modified as a VCO with programmable tail currents is introduced herein. The VCO is implemented by using CMOS current-mode logic stages, which are based on differential pairs that are connected in a ring topology. SPICE simulation results show that the VCO operates within the frequency ranges of 2.65–5.65 GHz, and when it is modified, the VCO with programmable tail currents operates between 1.38 GHz and 4.72 GHz. The design of the CMOS differential stage is detailed along with the symbolic approximation of its dominant pole, which is varied to increase the frequency response in order to achieve a higher oscillation frequency when implementing the ring oscillator structure. The layout of the VCO is described and pre- and post-layout simulations are provided, which are in good agreement using CMOS technology of 180 nm. Finally, process, voltage and temperature variations are performed to guarantee robustness of the designed CMOS ring oscillator.
Highlights
Current mode logic (CML) was used as a mean to design VLSI logic gates to accomplish nanosecond delays
current mode logic (CML) emerged with bipolar junction transistors (BJT) [1], and the aim was focused on eliminating the emitter-coupled logic (ECL) drawbacks at that time, such as large power consumption and excessive heat generation [2]
This article introduces the design of a wide-band voltage-controlled oscillator (VCO) that is implemented using CML stages connected in a ring topology
Summary
Current mode logic (CML) was used as a mean to design VLSI logic gates to accomplish nanosecond delays. Several CML blocks have been used for the implementation of various topologies and logic gates, such as, buffers, latches, flip-flops, XOR gates, and push–pull topologies, among others In this manner, this article introduces the design of a wide-band voltage-controlled oscillator (VCO) that is implemented using CML stages connected in a ring topology. Other desired features in designing a VCO are associated to accomplish low-power consumption, minimum layout area, large output frequency range and wide tuning range. The main effects are that decreasing N yields a reduction in gain, which may result in the oscillation eventually stopping In this manner, this article shows that deriving the symbolic approximation of the dominant pole of the CMOS CML stage, through the use of the high-frequency small-signal equivalent model of the MOS transistor [17], can help to enhance the oscillation frequency.
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