Design of a Two Stage CMOS Operational Amplifier in 100nm Technology with Low Offset Voltage

Abstract

The motive of our study is to design a two-stage CMOS operational amplifier with low input offset voltage. Basically, an operational amplifier (op-amp) has two different inputs and one output. The output voltage signal of an op-amp is the distinction between the applied signals of its two separate inputs. This implies that if there is no difference between the two inputs, there will be no voltage on the output. But practically there is always a little input offset voltage because of the mismatch of the circuit components which restricts some of its applications. In this paper, the offset error has been reduced through improving the phase margin of a two-stage CMOS opamp using compensation capacitor connected in parallel with the second stage of the op-amp. Miller theorem has been applied while connecting the capacitor to reduce the power consumption; therefore, we have designed the MOSFETs according to the improved phase margin. Matching property of the MOSFETs has been also used when designing the circuit. The achieved results show that offset error is reduced after the modification. This study may be useful in DC amplifiers where this small error can be significant because of the large gain of the circuit.