Abstract
A tunable reference clock frequency topology is presented as a spur reduction application for frequency synthesizers of fast frequency hopping spread spectrum systems. The method was verified by measurements on a designed hardware operating at L-band frequencies. This spur reduction method is based on optimizing the reference clock frequency of synthesizers to mitigate spurs. By using the spur reduction method, the power of spurious signals was reduced up to 57 dB. The performance of the spur reduction method was also analyzed at different loop-filter configurations. Smaller lock time was obtained by enlarging the bandwidth of the loop filter up to 150 kHz. The required power response of the spurious signals specified in telecommunication standards was achieved even though the loop filter bandwidth was enlarged.
Highlights
A frequency synthesizer is a critical section of an intermediate frequency (IF)-based receiver design in terms of both local oscillator signal generation and the analog-to-digital conversion section
The receiver performance is directly affected by clock phase noise and accuracy properties because the reduction in signal-to-noise ratio and the effective number of bits in the analog-digital converter (ADC) section is caused by poor phase noise and signal frequency accuracy properties
An adjacent channel or an interference can exist in the same span, which is very close to the desired signal and has a higher power response than the desired signal
Summary
A frequency synthesizer is a critical section of an intermediate frequency (IF)-based receiver design in terms of both local oscillator signal generation and the analog-to-digital conversion section. High-efficiency spectrum applications can be achieved by smaller tuning step size properties of fractional type PLLs. the spurious response is caused by the PLL operation itself. The spurious response of the PLL is caused by reference clock properties and fractional type PLL operation. The comparator is fed by a reference clock signal and the clock signal is obtained by dividing the VCO frequency by a feedback divider. The feedback divider ratio includes the fractional part to obtain a smaller step size. The feedback divider ratio is changed between N and N+1 by the modulator to attain the fractional part of the frequency. The phase noise reduction problem is eliminated due to higher PFD frequencies in fractional PLL topology. The fractional spur location can be specified by the PFD frequency and feedback divider ratio. Poor lock times are caused by narrow loop filters. [1, 2]
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