Design of a solid state fault isolation device for implementation in power electronics based distribution systems

Abstract

This paper addresses the timely issues of modeling of, and defining selection criteria for, a solid state fault isolation device (SSFID) to be used in power electronic based distribution systems. The paper derives the SSFID parameters by mapping the characteristics of a conventional medium-voltage distribution system onto that of the power electronic based Future Renewable Electric Energy Delivery and Management (FREEDM) system envisioned under a new multi-university Engineering Research Center funded by the National Science Foundation. Major drawbacks of all SSFID solutions presented so far are material costs and on-state losses. Power semiconductor devices are briefly compared considering the requirements of a solid state switch integrated into a 15 kV class medium voltage grid. A design of a high frequency Solid State Transformer (SST) is presented and evaluated. The simulation results verify the functionality and feasibility of SST. Utilizing an average-value simulation model of a SST, as the interface of the power electronics based distribution system to the legacy system, is used to derive key parameters of the SSFID. Circuit interruption requirements and SSFID location in power electronics based distribution system are discussed in this paper. The simulation and experimental results in low voltage single phase system validated the feasibility of the proposed SSFID topology. Finally, the conceptual Power Hardware-in-the-Loop setup for SSFID testing is presented and discussed in this paper.