Design of a Small-Offset 12-Bit CMOS DAC Using Weighted Mean Sample-and-Hold Circuit

Abstract

This paper describes the design of a small-offset 12-bit CMOS charge-redistribution DAC using a weighted-mean flip-around sample-and-hold circuit (S/H). Flip-around S/H topology can realize small-offset characteristics, and it is effective to reduce power dissipation and chip area because independent feedback capacitors are not necessary. In this DAC the small-offset characteristic remains not only in amplification phase but also in sampling phase with the circuit technique. The design of 1.8 V, 50 MS/s fully differential DAC with output swing of 2 Vp-p has very small offset of 100μV for the reset switch mismatch of 2%. A technique to improve dynamic performance measured by SFDR using damping resistors and switches at the output stage is also presented. The designed 12-bit DAC with 0.25μm CMOS technology has low-power dissipation of 35 mW at 50 MS/s.