Design of a single flux quantum Σ– Δ A/D converter with a ladder circuit as an on-chip-clock-generating circuit

Abstract

We investigated an oversampling Σ– Δ A/D converter (ADC) with a large signal-to-noise ratio (∼80 dB or more) and a wide bandwidth (∼100 MHz), which were formed from single flux quantum circuits. The ADC consisted of a second-order lowpass Σ– Δ modulator and a third-order sinc decimation filter. A ladder circuit was utilized to supply the high frequency sampling clock signal of more than 16 GHz to the modulator. The third-order sinc filter was designed from a multistage decimation sinc filter and a multiple integration sinc filter. By combining both sinc filters, the sinc filter operating with a decimation factor of 16 at the high clock frequency of more than 16 GHz could be designed in the chip area of ∼10 × 10 mm 2. Experimentally, we measured the bit rate of the ladder circuit from an average voltage measurement and an oscilloscope observation, and obtained the bit rate of 31 Gbps.