Design of a scalable pipelined RAM system

Abstract

This paper describes a scalable pipelined RAM system (SPRAMS) for packet switching. The SPRAMS consists of a two-dimensional array of small memory blocks which are fully pipelined and communicate with adjacent blocks in three directions. The maximum delay of a small memory block becomes the cycle time of the chip. The array configuration is scalable for large memory size without the cycle time variation. It has an initial latency of N+3 cycles with an N/spl times/N array configuration. We have designed an experimental 200 MHz 4 kbit static RAM chip with the 4/spl times/4 array configuration of 256 bit SRAM blocks. It was fabricated in 0.8 /spl mu/m single-poly double-metal CMOS technology. Experimental results describe the advantages of SPRAMS.