Design of a prototype analog front-end ASIC for the LGAD readout

Abstract

Low-gain avalanche detector (LGAD) is being researched and designed in ATLAS and CMS experiments aiming to distinguish collisions that are close in both space and time to meet the challenge of pileup in HL-LHC, through its high resolution in position and time measurement. Considering the high spatial density of the detector channels, the area and power consumption per each channel are quite limited, so a front-end ASIC, instead of discrete-component electronics, is expected to collect and process the signal output by the LGAD. The processed signal is a digital pulse containing the precise information of time of arrival (TOA) and time over threshold (TOT). A prototype analog front-end ASIC for LGAD readout based on 180 nm CMOS technology with low power consumption, called LATIC0, has been designed and tested. As the first prototype, this ASIC aims to study the performance of the analog front-end for the further work. And the test results indicate that a time precision better than 20 ps-rms is achieved (at 10 fC injected charge with 6 pF capacitance), and the curves of TOA and TOT versus charge concord well with expectations.