Abstract
A 15 GHz power amplifier design for 5G applications is presented in this paper. The proposed power amplifier consists in a three-stage architecture. A low complex pre-distortion circuit is designed as the first stage. Since the CMOS process suffers from poor intrinsic gain (gm*ro), especially in the millimeter wave band, the Darlington pair driver stage is exploited to maximize the power gain. A FET-stack structure is used to enable high voltage operation and thus increase the output power. The proposed power amplifier is designed and simulated in a standard 130nm CMOS process. The simulation results show that the proposed power amplifier can attain 1dB compression point (P 1dB ) of 18.9 dBm with a power added efficiency (PAE) of 26% under 3.6 V and 1.8 V dual voltage supply.
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