Abstract
Complementary Metal Oxide Semiconductor (CMOS) technology uses voltage levels for binary computation, whereas Quantum Dot-Cellular Automata (QCA) uses free electron location in the QCA cell for logic evaluation. This technology suggests very low power consumption, high speed and very dense structure for performing any logical circuit. Reversible logic is best mechanism with low power and high speed in circuit designing. Reversible gates have N input and N output lines that input lines mapped with output lines one by one. In this paper, a novel design of Reversible Full adder/subtractor with minimum number of cells has been proposed. QCADesigner software has been used to simulate the proposed design.
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