Design of a Mathematical Unit in FPGA for the Implementation of the Control of a Magnetic Levitation System

Juan José Raygoza-Panduro,Susana Ortega-Cisneros,Alberto De La Mora,Jorge Rivera

doi:10.1155/2008/634306

Juan José Raygoza-Panduro, Susana Ortega-Cisneros + Show 2 more

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https://doi.org/10.1155/2008/634306

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Abstract

This paper presents the design and implementation of an automatically generated mathematical unit, from a program developed in Java that describes the VHDL circuit, ready to be synthesized with the Xilinx ISE tool. The core contains diverse complex operations such as mathematical functions including sine and cosine, among others. The proposed unit is used to synthesize a sliding mode controller for a magnetic levitation system. This kind of systems is used in industrial applications requiring high level of mathematical calculations in small time periods. The core is designed to calculate trigonometric and arithmetic operations in such a way that each function is performed in a clock cycle. In this paper, the results of the mathematical core are shown in terms of implementation, utilization, and application to control a magnetic levitation system.

Highlights

Mathematical control equations in an FPGA reconfigurable device is an important aspect in the design of arithmetic blocks when implementing control algorithms [1]
A wellknown method utilized in the implementation of arithmetic operations in FPGAs is based upon the coordinate rotation digital computer (CORDIC) algorithm [2,3,4,5,6] which has become the standard solution for the implementation of complex operations in FPGAs
This paper proposes the design of a mathematical unit dedicated to the implementation of control algorithms that involve several sequences of complex mathematical functions calculations

Summary

Introduction

Mathematical control equations in an FPGA reconfigurable device is an important aspect in the design of arithmetic blocks when implementing control algorithms [1]. The development of complex arithmetic functions in FPGA devices has resulted in difficulties to implement such operations. The elaboration of mathematical operations in Xilinx FPGAs is proposed through the core generator [7]. The objective of this paper is to explain the development of a core capable of performing mathematical operations such as trigonometric functions in a clock cycle, using an alternative method of the core generator suggested by the manufacturer

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