Design of a low-voltage low power dynamic latch comparator for a 1.2-V 0.4-mW CT delta sigma modulator with 41-dBm SNDR

Abstract

In this paper the combination of inverter-based operational transconductance amplifier (OTA), dynamic latch comparator and switch capacitor based return to zero (SCRZ) DAC approach for a continuous time delta sigma modulation (CTDSM) are introduced. The inverter-based design of OTA is a novel approach for low voltage analog design. This architecture is taken into consideration for the high bandwidth operation, simple structure and the advantage of no additional voltage headroom. Dynamic latch comparator is suitable for design of CTDSM as it makes a stable comparator and gives full swing. SCRZ DAC is advantageous for low jitter sensitivity of Switch capacitor DAC and low distortion of RZ DAC. A second order CT-DSM is implemented with results showing 41dBm of SNDR, 51dBm SNR and 6.5 ENOB in 90nm CMOS technology with 1.2V supply voltage and 0.4mW power. The signal bandwidth is 4MHz and sampling frequency is 256MHz.