Design of a low‐power way‐predicting cache using valid‐bit pre‐decision strategy

Abstract

Way‐predicting cache is one of the set‐associative caches that can effectively reduce power consumption, which only speculatively selects an MRU (most recently used) way before starting a normal cache access. Focusing on the way‐predicting cache using sub‐block placement, we propose a new cache scheme that uses valid bits from data memory to decide the disabled tag‐subarrays and data‐subarrays. By using valid‐bit pre‐decision, the proposed scheme has a significant improvement in average energy saving over the conventional way‐predicting cache, especially for large associativity and small sub‐block size. Moreover, because those original second accessed ways are first accessed during the first cycle when the valid bit of the MRU way does not exist, the proposed cache also can reduce the average access time.