Abstract
In this paper, a novel 108-bit conditional sum adder(CSA) with Energy Economized Pass-transistor Logic(EEPL) is proposed. A new architecture is adopted, which is composed of seven modularized 16-bit CSA’s and two separated CARRY Generation Block. In order to obtain a high speed operation, the CARRY Generation Blocks are separated from the modularized CSA. Further, a design technique based on EEPL is proposed to reduce the power consumption. With 0.65μm single poly, triple metal 3.3V CMOS process, its operating speed is about 4.95ns and the power consumption is reduced in comparison with that of the conventional adder.
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