Design of a low noise, low power 3.05–3.45 GHz digitally controlled oscillator in 90 nm CMOS

Abstract

The design of a multi-GHz digitally controlled oscillator (DCO) achieving low noise and power consumption is presented. The DCO is part of an all-digital phase lock loop (ADPLL) for an FM-radio transmitter prototype chip designed in a 90 nm CMOS process. For this application the oscillator frequency of 3.05-3.45 GHz is divided by 32 or 36 to cover the frequency span of 87.5-108.0 MHz. A wide tuning range combined with a precise frequency tuning is achieved by different digitally controlled variable capacitors grouped as banks. Different approaches of these variable capacitors and oscillator topologies are simulated and compared. The design is chosen considering low phase noise combined with low power consumption. The power consumption of the designed DCO core is below 1.7 mW at 1 V supply voltage. This setup shows a phase noise below -154 dBc/Hz at 20 MHz offset. The chip area utilised by one DCO is 260 times 500 mum. Simulations show the performance of this DCO is state-of-the-art.