Design of a high throughput configurable variable-length FFT processor based on switch network architecture

Abstract

Fast Fourier transform (FFT) is one of the key operations in digital communication systems and digital signal processing platforms. This paper presents a design of high throughput variable-length FFT processor based on switch network (SN) architecture. Meanwhile, strong runtime configurability and scalability is exploited. Considering the support for variable-length FFT as well as the balance between speed and cost, the mixed-radix (MR) technique and in-place strategy are used. In addition, auto synchronization method is proposed to make stage pipelined mode work efficiently. Batch processing mode is also proposed to boost performance for small size FFTs. The results show that the throughput for 16-point to 256-point FFT can be improved from 5.8X to 1.2X, respectively. The processor supports 16- to 8192-point FFT and provides about 2GSamples/s for FFT size less than or equal to 256 by batch processing, and 1GSamples/s throughput for larger size FFT at 500MHz. The core area is 2.04 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the power consumption is 68 mW at 100MHz for 1k-point.