Design of a high-order single-loop ΣΔ ADC followed by a decimator in 0.18 μm CMOS technology

Abstract

This work presents an oversampled high-order single-loop single-bit sigma–delta analog-to-digital converter followed by a multi-stage decimation filter. Design details and measurement results for the whole chip are presented for a TSMC 0.18 μm CMOS implementation to achieve virtually ideal 16-b performance over a baseband of 640 kHz. The modulator in this work is a fully differential circuit that operates from a single 1.8 V power supply. With an oversampling ratio of 64 and a clock rate of 81.92 MHz, the modulator achieves a 94 dB dynamic range. The decimator achieves a pass-band ripple of less than 0.01 dB, a stop-band attenuation of 80 dB and a transition band from 640 to 740 kHz. The whole chip consumes only 56 mW for a 1.28 MHz output rate and occupies a die area of 1 × 2 mm2.