Design of a Generic Network on Chip Frame Work Using Wormhole Routing for 2D Mesh

Abstract

The requirements of high performance mega functional solutions are becoming important day by day. With the advancement in semiconductor devices and fabrication technology, it is possible to pack more logic in smaller area of silicon. But the implementation of these mega functional modules using common bus architecture, parallel bus architecture, pipelining are becoming ineffective and posing a bottleneck in terms of performance and throughput in this billion transistor era. To overcome these performance issues, a new paradigm in interconnect technology was proposed. The proposal is to implant the concept of data transfer in data communication networks providing advantages of low power scalable high performance architecture. This can be achieved with a small increase in silicon area, for routing resources. This paper discusses the design of a generic frame work for wormhole routing strategy for 2D mesh topology. It also discusses the data transfer operation and other aspects of this frame work.