Abstract
One of the most important elements in digital electronics is the full adder, which has made uninterrupted improvements to its structure in terms of speed, operating voltage, power consumption and chip area. In this paper, we present a low-power full adder cell utilizing the benefits of CNTFET, the main purpose of which is to provide high speed and low power consumption with full voltage swing. This new design works successfully at low voltages with the ability to drive properly. A comparison between this new circuit and modern full adder cells shows the improvement in terms of delay and power-delay product (PDP). The proposed design can work well at a supply voltage of 0.5 V with a delay of 33.971 ps, an average power consumption of 0.476 μW and a PDP of 16.19 aJ.
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