Design of a fault-tolerant multichannel ATM switch for BISDN

Abstract

One of the techniques to improve the throughput and the reliability of the ATM switch is to provide multiple channels for the cells destined to the same switching node. The performance advantages of multichannel switch architectures have been discussed in the literature (T.H. Cheng and D.G. Smith, Proc. ICC'91, pp. 1028–1032, A. Lin and J. Silvester, Proc. INFOCOM'90, pp. 803–810, A. Pattavina, IEEE J. Selected Areas Comm. SAC-6 (1988) 237–243 and L.T. Wu et al., 1988 International Zurich Seminar on Digital Communications, pp. 191–197). However, these switch architectures do not preserve the cell sequence thus requiring the end system to resequence the cells. In this paper, we introduce a multichannel ATM switch architecture that guarantees the cell sequence throughout the network when the channel grouping is used in the switching nodes. The switch consists of two modified banyan networks and a Batcher sorter (Batcher, AFIPS Proc. Spring Joint Comput. Conf., pp. 307–314, 1968). It is shown that the cell sequence will be preserved by providing a virtual FIFO queue within the switch architecture. The virtual FIFO queue is shared by all the input-output pairs so that the cell loss probability is significantly reduced. The switch has a distributed control and allows a large switch size without degrading the performance. Furthermore, a simple update of entries in the lookup table allows the fault-tolerant operation in the event of the link or node failure in the network. The performance analysis of the switch shows that the number of buffers and the average cell delay can be significantly reduced in the proposed switch while maintaining the required throughput and cell loss probability compared to the multichannel switches with dedicated buffers.