Design of a dynamically reconfigurable arithmetic unit for matrix algorithms

Abstract

Matrix operations, such as multiplication, inversion operations, are widely used in high-perforamce industrial control, scientific computing, and media processing applications. To meet the increasingly intensive timing and power demands of matrix opertions, dynamically reconfigurable structures are introduced as a new design paradigm to make a good balance between performance and flexibility. In this paper, a dynamically reconfigurable multi-operation arithmetic unit is proposed basing on multiply-add-fused unit. The proposed arithmetic unit consists of three pipeline stage, each of which can be dynamically configured by control signals. The proposed arithmetic unit can be used for addition, subtraction, multiplication and multiply-add-fused operations for different data types. Compared with the traditional arithmetic units, the chip area is reduced by the proposed unit since the most functional units are reused for different operations.