Design of a Digital Peak V2 Controller for the Synchronous Boost Converter with Negligible ESR

Abstract

Peak V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> control technique is widely used in the industry due to its simple loop compensation and improved load transient performance; however, its application is limited to the buck converter. Recently, valley V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> control technique is proposed for the boost converter. Stability of the controller is ESR dependant; large ESR provides better stability margin. However, a large ESR at the output is not desirable as it reduces efficiency and increases output voltage ripple. This paper proposes a digital peak V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> controller for the boost converter which works with negligible ESR. The proposed controller samples both the inductor current and output voltage at the rate of the switching frequency. Thus, digital implementation of this controller does not need high-speed ADC. An average model-based small-signal model of the proposed controller is presented. The small-signal model is used for slow-scale stability analysis and voltage-loop controller tuning. Analysis shows that the stability of the boost converter depends on the current-loop gain. Furthermore, fast-scale stability analysis of the controller is carried out using an approximate discrete-time model to derive an analytical stability boundary of slope compensation. A boost converter prototype is built and the proposed controller is implemented in an FPGA device. Experimental results closely match with the analytical predictions.