Design of a delay-insensitive multiply-accumulate unit

Abstract

This paper describes the design and implementation of a serial-parallel multiply-accumulate unit using the method and tools developed at Caltech for the design of delay-insensitive circuits. In this class of asynchronous circuits the functional correctness is independent of any delays in circuit elements and wires except for certain known isochronic forks. An objective in asynchronous design is to attain the best possible average performance and to use this potential performance advantage already at the architectural level. The multiply-accumulate unit is designed to exploit these advantages. We illustrate the full course of design from a high-level description to fabrication including optimization considerations at each level of the design.