Design of a Configurable Five-Stage Pipeline Processor Core Based on RV32IM

Abstract

With the rapid development of the electronics industry, the scale of the global Internet of Things (IoT) industry has shown an exponential growth trend in recent years. The huge demand for IoT equipment makes low cost an important indicator for the sustainable operation of the entire IoT system. However, IoT chips also require a certain amount of performance to perform complex tasks. Aiming at the above contradiction between performance and cost, this paper proposes a configurable five-stage pipeline processor core based on RV32IM. The proposed processor core has multiple configurable modules to suit different application scenarios. In low-power mode, the proposed architecture implements only an RV32I subset, while in high-performance mode, integer division and multiplication extensions are added. Meanwhile, the processor core will also support super and user privilege levels and is equipped with CSR (Control and Status Registers). The module-level and system-level simulations of the proposed architecture are completed using a fully open-source workflow based on verilator and gtkwave. In addition, the design was prototyped and verified with FPGA. The proposed processor outperforms the performance of the classic MCU-CortexM3.